module DMem(clkIn,resetIn,AddrIn,DataIn,ReadIn,WriteIn,DataOut);
  input clkIn;
  input resetIn;
  input [31:0]AddrIn;
  input [31:0]DataIn;
  input ReadIn;
  input WriteIn;
  output [31:0]DataOut;

  integer i;
  reg[31:0] RAM[31:0];
  always@(posedge clkIn or negedge resetIn)begin
    if(!resetIn)begin
      for (i = 0;i<32 ;i=i+1 ) begin
         RAM[i]<=0;
      end
    end
    else begin
        if(WriteIn)
          RAM[AddrIn]<=DataIn;
    end
  end
  assign DataOut=ReadIn?RAM[AddrIn]:0;
endmodule
